The present invention relates to self-aligned double patterning (SADP), and more specifically, to metal fill optimization for SADP.
The back-end-of-line (BEOL) is the second portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, i.e., the metallization layer. Common metals that are used to form the metallization layers and interconnects are copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. The SADP process is typically part of the BEOL process.